lazagna package

Submodules

lazagna.arch_xml_modification module

lazagna.csv_locations_generator module

lazagna.file_handling module

lazagna.main module

lazagna.printing module

lazagna.printing.print_verbose(*args, **kwargs)

lazagna.run_flow module

lazagna.run_flow.copy_results(original_dir, task_result_path, results_path, result_name, temp_dir='')

lazagna.run_flow.create_base_rrg(original_dir: str, path_to_arch: str, channel_width=2, path_to_write_rrg='/base_rrg/rr_graph.xml', path_to_benchmark='/benchmarks/and2/and2.blif')

lazagna.run_flow.create_custom_3d_rrg(base_arch_path, output_file_path, original_dir, percent_connectivity=0.5, connection_type='subset', arch_file='', vertical_connectivity=1, sb_switch_name='', sb_segment_name='', sb_input_pattern=[], sb_output_pattern=[], sb_location_pattern='repeated_interval', sb_grid_csv_path='')

lazagna.run_flow.run_command_in_temp_dir(command, original_dir, handle_error=True, verbose=False)

Run a command in a temporary directory.

Parameters:

• command (list) – Command to execute

• original_dir (str) – Original working directory

Returns:

Result of the command execution

Return type:

subprocess.CompletedProcess

lazagna.run_flow.run_flow(original_dir, width, height, channel_width, benchmark_name='', temp_dir='', type_sb='full', arch_path='', rrg_3d_path='', percent_connectivity=0.5, place_algorithm='cube_bb', connection_type='subset', run_num=1, output_additional_info='')

lazagna.run_flow.run_task(original_dir, temp_dir='')

lazagna.run_flow.setup_flow(original_dir, width, height, channel_width, type_sb='full', percent_connectivity=0.5, place_algorithm='cube_bb', is_verilog_benchmarks=False, connection_type='subset', arch_file='', random_seed=1, run_num=1, extra_vpr_options='', output_additional_info='', temp_dir='', vertical_connectivity=1, sb_switch_name='', sb_segment_name='', sb_input_pattern=[], sb_output_pattern=[], sb_location_pattern='repeated_interval', sb_grid_csv_path='', vertical_delay_ratio=1, sb_3d_switch_name='3D_SB_switch', base_delay_switch='', switch_interlayer_pairs={}, update_arch_delay=False)

lazagna.run_interface module

lazagna.run_interface.main()

lazagna.run_interface.run_interface(params)

Run the interface with parameters from a dictionary.

lazagna.run_interface.run_one_benchmark(i, blif_file='', verilog_file='', act_file='', original_dir='', width='', height='', channel_width='', type_sb='full', percent_connectivity=0.5, place_algorithm='cube_bb', verilog_benchmarks=False, connection_type='subset', benchmark_top_name='', output_folder_name='', run_number=1, output_additional_info='', temp_template_dir='')

lazagna.script_editing module

lazagna.script_editing.append_cw_to_script(file_path, string_to_add)

Appends the Channel width to the line that starts with ‘vpr’ in the script file.

Parameters:

• file_path (str) – Path to the file to modify.

• string_to_add (str) – String to append to the ‘vpr’ line.

lazagna.script_editing.append_extra_vpr_option_to_script(script_path, string_to_add)

lazagna.script_editing.append_place_algorithm_to_script(script_path, place_algorithm='cube_bb')

lazagna.script_editing.append_random_seed_to_script(script_path, random_seed)

lazagna.script_editing.append_rrg_to_script(script_path, rrg_path)

lazagna.script_editing.update_config_simple(config_path, benchmark_blif, benchmark_name, benchmark_act, benchmark_verilog)

Updates specific keys in the configuration file: ‘bench0’, ‘bench0_top’, ‘bench0_act’, and ‘bench0_verilog’.

Parameters:

• config_path (str) – Path to the configuration file.

• bench_file (str) – New value for ‘bench0’.

• bench_top (str) – New value for ‘bench0_top’.

• bench_act (str) – New value for ‘bench0_act’.

• bench_verilog (str) – New value for ‘bench0_verilog’.

lazagna.script_editing.update_config_verilog(config_path, benchmark_verilog, benchmark_top_name)

lazagna.split_top_module module

lazagna.split_top_module.collect_instances(lines)

Scan for ANY instantiation that contains ‘_layer_<N>_’ in its module or instance name, grab the entire block from the line with the ‘(’ down through the matching ‘);’

lazagna.split_top_module.collect_wires(lines)

Return dict wire_name -> declaration line

lazagna.split_top_module.debug_dump_head(lines, n=10)

lazagna.split_top_module.extract_global_ports(lines)

1. Gather all lines between ‘module fpga_top(’ and the matching ‘);’

2. Split on commas to get the ordered list of port names

3. For each port name, find its input/output/inout declaration elsewhere and record (direction, name, width)

lazagna.split_top_module.find_cross_wires(insts_by_layer)

Build a map net -> set(layers) by scanning all ‘(net)’ occurrences in each instance. A net is cross-layer if it shows up in >=2 layers.

lazagna.split_top_module.find_layers(lines)

Return sorted list of layer‐IDs found in any wire or instance name.

lazagna.split_top_module.group_insts_by_layer(instances)

lazagna.split_top_module.group_wires_by_layer(wires)

lazagna.split_top_module.layer_of_name(name)

Return layer id embedded in name, or None.

lazagna.split_top_module.make_submodule(layer, wires, instances, cross_wires, cross_sizes, global_ports)

Generate the text of fpga_layer_{layer}.v

• global_ports is a list of (direction, name, width) from the original top module

lazagna.split_top_module.read_file(fn)

lazagna.split_top_module.write_file(fn, lines)

lazagna.yaml_file_processing module

lazagna.yaml_file_processing.combinations_contains_duplicates(combinations)

lazagna.yaml_file_processing.generate_param_combinations(param_ranges: Dict) → List[Dict]

Generate all possible parameter combinations

lazagna.yaml_file_processing.generate_seed_mapping(num_seeds: int) → List[Dict]

Generate seed and run number mapping

lazagna.yaml_file_processing.get_run_params_from_yaml(file_path, verbose=False)

Load parameters from a YAML file and generate all combinations.

lazagna.yaml_file_processing.is_multi_option(value: Any) → bool

Check if a parameter has multiple options to try

lazagna.yaml_file_processing.load_param_ranges(yaml_file: str) → Dict

Load parameter ranges from YAML file and optionally add seed mapping

lazagna.yaml_file_processing.print_combinations(combinations)

Module contents